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EM342-RTR Datasheet(PDF) 106 Page - Silicon Laboratories

Part # EM342-RTR
Description  High-Performance, Integrated RF4CE System-on-Chip
PDF  143 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

EM342-RTR Datasheet(HTML) 106 Page - Silicon Laboratories

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EM342
106
Rev 1.0
9.5. Registers
Address: 0xE000E100; Reset: 0x0
Register 9.1. INT_CFGSET: Top-Level Set Interrupts Configuration Register
Bit
31
30
29
28
27
26
25
24
Name
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Name
0
0
0
0
0
0
0
INT_DEBUG
Bit
15
14
13
12
11
10
9
8
Name INT_IRQD INT_IRQC Reserved
INT_IRQA
Reserved
INT_MACRX INT_MACTX INT_MACTMR
Bit
7
6
5
4
3
2
1
0
Name INT_SEC
Reserved
INT_SC1
INT_SLEEPTMR
INT_BB
INT_MGMT
Reserved
Reserved
Bit Name
Bit Field
Access
Description
INT_DEBUG
[16]
RW
Write 1 to enable debug interrupt. (Writing 0 has no effect.)
INT_IRQD
[15]
RW
Write 1 to enable IRQD interrupt. (Writing 0 has no effect.)
INT_IRQC
[14]
RW
Write 1 to enable IRQC interrupt. (Writing 0 has no effect.)
INT_IRQA
[12]
RW
Write 1 to enable IRQA interrupt. (Writing 0 has no effect.)
INT_MACRX
[10]
RW
Write 1 to enable MAC receive interrupt. (Writing 0 has no effect.)
INT_MACTX
[9]
RW
Write 1 to enable MAC transmit interrupt. (Writing 0 has no effect.)
INT_MACTMR
[8]
RW
Write 1 to enable MAC timer interrupt. (Writing 0 has no effect.)
INT_SEC
[7]
RW
Write 1 to enable security interrupt. (Writing 0 has no effect.)
INT_SC1
[5]
RW
Write 1 to enable serial controller 1 interrupt. (Writing 0 has no effect.)
INT_SLEEPTMR
[4]
RW
Write 1 to enable sleep timer interrupt. (Writing 0 has no effect.)
INT_BB
[3]
RW
Write 1 to enable baseband interrupt. (Writing 0 has no effect.)
INT_MGMT
[2]
RW
Write 1 to enable management interrupt. (Writing 0 has no effect.)



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