PC87373 datasheet(33/174 Pages) NSC

33 / 174 page

2.0 Power, Reset and Clocks (Continued)

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Revision 1.1

2.4.2

XOR Tree Testing

When the PC87373 device is mounted on a board, it can be tested using the XOR Tree technique. This test also checks the

correct connection of the device pins to the board.

To enter XOR Tree mode, the TEST pin must be pulled low (by a 10 K

Ω resistor to V

SS), and the TRIS pin must be left

unconnected after both VDD3 and VSB3 power supplies are turned on. In addition, the PCI_RESET pin must be held low for

at least 10 ms (see VSB Power-Up Reset on page 159 and VDD Power-Up Reset on page 160). After PCI_RESET is de-

asserted, the device pins (including the PCI_RESET, TRIS and TEST pins) are connected in a XOR Tree configuration and

are isolated from the internal PC87373 functions.

In XOR Tree mode, all PC87373 device pins are configured as inputs, except the last pin in the tree, which is the XOR_OUT

output. The buffer type of the input pins participating in the XOR tree, is INT (Input, TTL compatible), regardless of the buffer

type of these pins in normal device operation mode (see Section 1.4 on page 16). The input pins are chained through XOR

gates, as shown in Figure 4. The power supply pins (VDD3,VSB3,VSS,VCORF,VBAT), the analog pins (VSB5, REF5V,

REF5V_STBY), RSMRST are excluded from the XOR tree.

Figure 4. XOR Tree (Simpliﬁed Diagram)

The XOR tree starts with pin 32, continues incrementally with pin 33 (the next pin in ascending order) through pins 128, 1,

and 28, and ends with pin 30 (XOR_OUT).

The maximum propagation delay through the XOR tree, from pin 32 to XOR_OUT is TBD.

VSUP

Pin 32

XOR_OUT

Pin 33

Pin 28

Pin 30

Pin 1

Pin 128

. . .

PC87373 Datasheet(PDF) 33 Page - National Semiconductor (TI)