PC87373 datasheet(70/174 Pages) NSC

70 / 174 page

3.0 Device Architecture and Configuration (Continued)

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3.16 GAME PORT (GMP) CONFIGURATION

3.16.1 Logical Device B (GMP) Configuration

Table 27 lists the configuration registers that affect the Game Port. Only the last register (F0h) is described here. See Sec-

tion 3.2.3 on page 36 for descriptions of the other configuration registers. All of these registers are VDD3 powered.

Table 27. GMP Conﬁguration Registers

3.16.2 Game Port Configuration Register

This register is reset by hardware to 00h.

Power Well: VDD3

Location:

Index F0h

Type:

R/W

Index

Conﬁguration Register or Action

Type

Power Well

Reset

30h Activate (see Section 3.3.1 on page 40)

R/W

VDD3

00h

60h Base Address MSB register

R/W

VDD3

02h

61h Base Address LSB register

R/W

VDD3

01h

70h Interrupt Number and Wake-Up on IRQ Enable register

VDD3

00h

71h Interrupt Type

VDD3

03h

74h Report no DMA Assignment

VDD3

04h

75h Report no DMA Assignment

VDD3

04h

F0h Game Port Conﬁguration register

R/W

VDD3

00h

Bit

76543210

Name

Reserved

DBNC_EN

Reserved

INT_PU_EN

Reserved

TRI-STATE

Control

Reset

00000000

Bit

Description

7-5

Reserved.

DBNC_EN (Debounce Enable). When set to 1, this bit enables a 16 ms input debouncer on the Button 0 and

Button 1 input pins of Device A and Device B (pins 3V_DDCSCL/GPIOE13/JYABT0,

5V_DDCSCL/GPIOE11/JYABT1, 3V_DDCSDA/GPIOE12/JYBBT0, 5V_DDCSDA/GPIOE10/JYBBT1).

0: Disabled (default)

1: Enabled

Reserved.

INT_PU_EN (Internal Pull-Up Enable). When the GMP functionality is selected, this bit controls the internal

pull-up resistor on pins 3V_DDCSCL/GPIOE13/JYABT0, 5V_DDCSCL/GPIOE11/JYABT1,

3V_DDCSDA/GPIOE12/JYBBT0, 5V_DDCSDA/GPIOE10/JYBBT1.

0: Disabled (default)

1: Enabled

Reserved.

TRI-STATE Control. When the bit is set and the GMP is inactive, the GMP output pins are in TRI-STATE.

0: Disabled (default)

1: Enabled

PC87373 Datasheet(PDF) 70 Page - National Semiconductor (TI)

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