PC87373 datasheet(54/174 Pages) NSC

54 / 174 page

3.0 Device Architecture and Configuration (Continued)

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Revision 1.1

3.9.4

Parallel Port Modified Configuration Register

This register is reset to 07h.

Power Well: VDD3

Location:

Index F8h

Type:

R/W

Bit

76543210

Name

Reserved

Parallel Port Mode Select

Reset

00000111

Bit

Description

7-4

Reserved.

3-0

Parallel Port Mode Select. The mode selected by writing to these bits, is reﬂected by bits 7-5 in the Parallel

Port Standard Conﬁguration Register (see Section 3.9.3 on page 53).

Bits

3 2 1 0

Mode

0001:

SPP Extended mode. PD7-0 direction is controlled by software

0010:

EPP 1.9 mode

0100:

ECP mode (IEEE1284 register set), with no support for EPP mode

1000:

SPP-Compatible mode. PD7-0 are always output signals

0111:

ECP mode (IEEE1284 register set), with EPP mode selectable as mode “0100” (default)

1010:

EPP 1.7 mode

Other:

Reserved (writing a reserved value causes unpredictable behavior of the Parallel Port)

Selection of EPP 1.7 or 1.9 in ECP mode “0100” is controlled by bit 4 of Control2 conﬁguration register of the

Parallel Port at offset 02h.

Note: Before setting bits 3-0, enable the Parallel Port and set CTR/DCR (at base address + 2) to C4h.

PC87373 Datasheet(PDF) 54 Page - National Semiconductor (TI)

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