EM342-RTR datasheet(126/143 Pages) SILABS

126 / 143 page

EM342

126

Rev 1.0

PC1

I/O

Digital I/O

SWO

(see also Pin 33)

Serial Wire Output asynchronous trace output to debugger

Select asynchronous trace interface in ARM core

Enable trace interface in ARM core

Select alternate output function with GPIO_PCCFGL[7:4]

TRACEDATA0

Synchronous CPU trace data bit 0

Select 1-, 2- or 4-wire synchronous trace interface in ARM core

Enable trace interface in ARM core

Select alternate output function with GPIO_PCCFGL[7:4]

VDD_MEM

Power

1.8 V supply (flash, RAM)

PC0

I/O

High

current

Digital I/O

Either enable with GPIO_DBGCFG[5],



or enable Serial Wire mode (see JTMS description, Pin 35) and disable

TRACEDATA1

JRST

JTAG reset input from debugger

Selected when in JTAG mode (default mode, see JTMS description) and

TRACEDATA1 is disabled

Internal pull-up is enabled

IRQD

Default external interrupt source D.

IRQC and IRQD external interrupts can be mapped to any digital I/O pin

using the GPIO_IRQSEL and GPIO_IRQDSEL registers.

TRACEDATA1

Synchronous CPU trace data bit 1

Select 2- or 4-wire synchronous trace interface in ARM core

Enable trace interface in ARM core

Select alternate output function with GPIO_PCCFGL[3:0]

Do not connect

VDD_CORE

Power

1.25 V digital core supply decoupling

VDD_PRE

Power

1.8 V prescaler supply

VDD_SYNTH

Power

1.8 V synthesizer supply

OSCB

I/O

24 MHz crystal oscillator or left open when using external clock input on

OSCA

Table 17.1. EM342 Pin Descriptions (Continued)

Pin #

Signal

Direction

Description

EM342-RTR Datasheet(PDF) 126 Page - Silicon Laboratories

EM342-RTR Datasheet(HTML) 126 Page - Silicon Laboratories

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