EM342-RTR datasheet(125/143 Pages) SILABS

125 / 143 page

EM342

Rev 1.0

125

PC2

I/O

Digital I/O

Enable with GPIO_DBGCFG[5]

JTDO

JTAG data out to debugger

Selected when in JTAG mode (default mode, see JTMS description,

Pin 35)

SWO

Serial Wire Output asynchronous trace output to debugger

Select asynchronous trace interface in ARM core

Enable trace interface in ARM core

Select alternate output function with GPIO_PCCFGL[11:8]

Enable Serial Wire mode (see JTMS description, Pin 35)

Internal pull-up is enabled

PC3

I/O

Digital I/O

Either Enable with GPIO_DBGCFG[5],



or enable Serial Wire mode (see JTMS description)

JTDI

JTAG data in from debugger

Selected when in JTAG mode (default mode, see JTMS description,

Pin 35)

Internal pull-up is enabled

PC4

I/O

Digital I/O

Enable with GPIO_DBGCFG[5]

JTMS

JTAG mode select from debugger

Selected when in JTAG mode (default mode)

JTAG mode is enabled after power-up or by forcing nRESET low

Select Serial Wire mode using the ARM-defined protocol through a debug-

ger

Internal pull-up is enabled

SWDIO

I/O

Serial Wire bidirectional data to/from debugger

Enable Serial Wire mode (see JTMS description)

Select Serial Wire mode using the ARM-defined protocol through a debug-

ger

Internal pull-up is enabled

PB0

I/O

Digital I/O

IRQA

External interrupt source A

TRACECLK

Synchronous CPU trace clock

Enable trace interface in ARM core

Select alternate output function with GPIO_PBCFGL[3:0]

VDD_PADS

Power

Pads supply (2.1–3.6 V)

Table 17.1. EM342 Pin Descriptions (Continued)

Pin #

Signal

Direction

Description

EM342-RTR Datasheet(PDF) 125 Page - Silicon Laboratories

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