EM342-RTR datasheet(119/143 Pages) SILABS

119 / 143 page

EM342

Rev 1.0

119

15. Serial Wire and JTAG (SWJ) Interface

The EM342 includes a standard Serial Wire and JTAG (SWJ) Interface. The SWJ is the primary debug and

programming interface of the EM342. The SWJ gives debug tools access to the internal buses of the EM342 and

allows for non-intrusive memory and register access as well as CPU halt-step style debugging. Therefore, any

design implementing the EM342 should make the SWJ signals readily available.

Serial Wire is an ARM® standard, bidirectional, two-wire protocol designed to replace JTAG and provides all the

normal JTAG debug and test functionality. JTAG is a standard five-wire protocol providing debug and test

functionality. In addition, the two Serial Wire signals (SWDIO and SWCLK) are overlaid on two of the JTAG signals

(JTMS and JTCK). This keeps the design compact and allows debug tools to switch between Serial Wire and JTAG

as needed, without changing pin connections.

While Serial Wire and JTAG offer the same debug and test functionality, Silicon Labs recommends Serial Wire.

Serial Wire uses only two pins instead of five, and offers a simple communication protocol, high performance data

rates, low power, built-in error detection, and protection from glitches.

The ARM CoreSight™ Debug Access Port (DAP) comprises the Serial Wire and JTAG Interface (SWJ). As

illustrated in Figure 15.1, the DAP includes two primary components: a debug port (the SWJ-DP) and an access

port (the AHB-AP). The SWJ-DP provides external debug access while the AHB-AP provides internal bus access.

An external debug tool connected to the EM342's debug pins communicates with the SWJ-DP. The SWJ-DP then

communicates with the AHB-AP. Finally, the AHB-AP communicates on the internal bus.

Figure 15.1. SWJ Block Diagram

Serial Wire and JTAG share five pins:



JRST



JTDO



JTDI



SWDIO/JTMS



SWCLK/JTCK

Note: The SWJ pins are forced functions, and their corresponding GPIO_PxCFGH/L configurations are overridden when the

EM342 resets. An application must disable all debug SWJ debug functionality to reclaim any of the four SWJ GPIOs:

PC0, PC2, PC3, and PC4.

Since these pins can be repurposed, refer to "17. Pin Definitions" on page 121 and "7.3. Forced Functions" on

page 50 for complete pin descriptions and configurations.

For further information on the SWJ, contact customer support for application notes and ARM® CoreSight™

documentation.

SWJ-DP

Select

SWJ-DAP

Interface

JTAG

Interface

Control and

AP Interface

Pins

AHB-AP

AHB

EM342-RTR Datasheet(PDF) 119 Page - Silicon Laboratories

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