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PC87373 Datasheet(PDF) 102 Page - National Semiconductor (TI) |
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PC87373 Datasheet(HTML) 102 Page - National Semiconductor (TI) |
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102 / 174 page  6.0 System Wake-Up Control (SWC) (Continued) 102 www.national.com Revision 1.1 6.4.8 General-Purpose Enable 1 Register 0 (GPE1_EN_0) This register contains “child” events 0-7 of the GPE1_EN register. The enable bits behave according to the Enable Bit definition in the ACPI Specification (i.e., the bit can be read or written by software). Power Well: VSB3 Location: Offset 0Ch Type: R/W 6.4.9 General-Purpose Enable 1 Register 1 (GPE1_EN_1) This register contains “child” events 8-15 of the GPE1_EN register. The enable bits behave according to the Enable Bit definition in the ACPI Specification (i.e., the bit can be read or written by software). Power Well: VSB3 Location: Offset 0Dh Type: R/W Bit 76543210 Name GPIOE07 _EN GPIOE06 _EN GPIOE05 _EN GPIOE04 _EN GPIOE03 _EN GPIOE02 _EN GPIOE01 _EN GPIOE00 _EN Reset 00000000 Bit Description 7 GPIOE07_EN (GPIOE07 Event Enable). Enables an active event at pin 7 of GPIOE Port 0 to set PME_STS bit in GPE1_STS register. 0: Disable event (default) 1: Enable event to set PME_STS 6-0 GPIOE06_EN to GPIOE00_EN (GPIOE06 to GPIOE00 Event Enable). Same as above for pins 6-0 of GPIOE Port 0. Bit 76543210 Name Reserved GPIOE13 _EN GPIOE12 _EN GPIOE11 _EN GPIOE10 _EN Reset 00000000 Bit Description 7-4 Reserved. 3 GPIOE13_EN (GPIOE13 Event Enable). Enables an active event at pin 3 of GPIOE Port 1 to set PME_STS bit in GPE1_STS register. 0: Disable event (default) 1: Enable event to set PME_STS 2-0 GPIOE12_EN to GPIOE10_EN (GPIOE12 to GPIOE10 Event Enable). Same as above for pins 2-0 of GPIOE Port 1. |
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