MB96F348CWCPMC-GSE2 datasheet(3/109 Pages) CYPRESS

3 / 109 page

MB96340 Series

Document Number: 002-04579 Rev. *A

Page 3 of 109

I2C

■ Up to 400 kbps

■ Master and Slave functionality, 8-bit and 10-bit addressing

A/D converter

■ SAR-type

■ 10-bit resolution

■ Signals interrupt on conversion end, single conversion mode, continuous conversion mode, stop conversion

mode, activation by software, external trigger or reload timer

A/D Converter Reference Volt-

age switch

■ 2 independent positive A/D converter reference voltages available

Reload Timers

■ 16-bit wide

■ Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral clock frequency

■ Event count function

Free Running Timers

■ Signals an interrupt on overflow, supports timer clear upon match with Output Compare (0, 4), Prescaler

with 1, 1/21, 1/22, 1/23, 1/24, 1/25, 1/26, 1/27,1/28 of peripheral clock frequency

Input Capture Units

■ 16-bit wide

■ Signals an interrupt upon external event

■ Rising edge, falling edge or rising & falling edge sensitive

Output Compare Units

■ 16-bit wide

■ Signals an interrupt when a match with 16-bit I/O Timer occurs

■ A pair of compare registers can be used to generate an output signal.

Programmable Pulse Genera-

tor

■ 16-bit down counter, cycle and duty setting registers

■ Interrupt at trigger, counter borrow and/or duty match

■ PWM operation and one-shot operation

■ Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock and Reload timer overflow

as clock input

■ Can be triggered by software or reload timer

Real Time Clock

■ Can be clocked either from sub oscillator (devices with part number suffix “W”), main oscillator or from the

RC oscillator

■ Facility to correct oscillation deviation of Sub clock or RC oscillator clock (clock calibration)

■ Read/write accessible second/minute/hour registers

■ Can signal interrupts every half second/second/minute/hour/day

■ Internal clock divider and prescaler provide exact 1s clock

External Interrupts

■ Edge sensitive or level sensitive

■ Interrupt mask and pending bit per channel

■ Each available CAN channel RX has an external interrupt for wake-up

■ Selected USART channels SIN have an external interrupt for wake-up

Non Maskable Interrupt

■ Disabled after reset

■ Once enabled, can not be disabled other than by reset.

■ Level high or level low sensitive

■ Pin shared with external interrupt 0.

External bus interface

■ 8-bit or 16-bit bidirectional data

■ Up to 24-bit addresses

■ 6 chip select signals

■ Multiplexed address/data lines

■ Wait state request

■ External bus master possible

■ Timing programmable

Feature

Description

MB96F348CWCPMC-GSE2 Datasheet(PDF) 3 Page - Cypress Semiconductor

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