GXM datasheet(77/244 Pages) NSC

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Processor Programming (Continued)

3.10.5 Exceptions in Real Mode

Many of the exceptions described in Table 3-29 on page

75 are not applicable in real mode. Exceptions 10, 11, and

14 do not occur in real mode. Other exceptions have

slightly different meanings in real mode as listed in Table

3-31.

3.10.6 Error Codes

When operating in protected mode, the following exceptions

generate a 16-bit error code:

• Double Fault

• Alignment Check

•Invalid TSS

• Segment Not Present

•Stack Fault

• General Protection Fault

• Page Fault

The error code format and bit definitions are shown in

Table 3-32. Bits [15:3] (selector index) are not meaningful

if the error code was generated as the result of a page

fault. The error code is always zero for double faults and

alignment check exceptions.

Table 3-31. Exception Changes in Real Mode

Vector

Number

Protected Mode

Function

Real Mode

Function

Double fault.

Interrupt table limit overrun.

Invalid TSS.

Does not occur.

Segment not

present.

Does not occur.

Stack fault.

SS segment limit overrun.

General protection

fault.

CS,DS, ES,FS, GS seg-

ment limit overrun. In pro-

tected mode, an error is

pushed. In real mode, no

error is pushed.

Page fault.

Does not occur.

Table 3-32. Error Codes

987

6543

Selector Index

Table 3-33. Error Code Bit Definitions

Fault

Type

Selector Index

(Bits 15:3)

S2 (Bit 2)

S1 (Bit 1)

S0 (Bit 0)

Page

Fault

Reserved.

Fault caused by:

0 = Not present page

1 = Page-level protection

violation

Fault occurred during:

0 = Read access

1= Writeaccess

Fault occurred during

0 = Supervisor access

1 = User access.

IDT Fault

Index of faulty IDT

selector.

Reserved

If = 1, exception occurred while

trying to invoke exception or

hardware interrupt handler.

Segment

Fault

Index of faulty

selector.

TI bit of faulty selector

If =1, exception occurred while

trying to invoke exception or

hardware interrupt handler.

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