GXM datasheet(98/244 Pages) NSC

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Revision 3.1

Integrated Functions (Continued)

4.1.5

Display Driver Instructions

The GXm processor has four instructions to access pro-

cessor core registers. Table 4-6 shows these instructions.

Adding CPU instructions does not create a compatibility

problem for applications that may depend on receiving

illegal opcode traps. The solution is to make these instruc-

tions generate an illegal opcode trap unless a compatibil-

ity bit is explicitly set. The GXm processor uses the

scratchpad size field (bits [3:2] in GCR, Index B8h) to

enable or disable all of the graphics instructions. If the

scratchpadsizebitsare zero,meaningthatnoneofthe

cache is defined as scratchpad, then hardware will

assume that the graphics controller is not being used and

the graphics instructions will be disabled. Any other

scratchpad size will enable all of the new instructions.

Note that the base address of the memory map in the

GCR register can still be set up to allow access to the

memory controller registers.

Table 4-6. Display Driver Instructions

Syntax

Opcode

Description

BB0_RESET

0F3A

Reset the BLT Buffer 0 pointer to the base.

BB1_RESET

0F3B

Reset the BLT Buffer 1 pointer to the base.

CPU_WRITE

0F3C

Write data to CPU internal register.

CPU_READ

0F3D

Read data from CPU internal register.

GXM Datasheet(PDF) 98 Page - National Semiconductor (TI)